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System designers are familiar with standard DDR4 RAM components but with the demands on increasing performance and decreasing power consumption in mobile products, LPDDR4 and its variation, LPDDR4X, have become the desired memory devices for in-vehicle infotainment, smartphones, tablets, and thin notebooks. Understanding the design specifications for LPDDR4 and LPDDR4X devices and their application conditions is critical to achieving successful system-level designs.
Like DDR4 memory requirements, the performance of LPDDR4 is measured by eye mask, jitter, and BER. In addition, LPDDR4 and 4X interfaces specify these measurements to both the data and address signals, with LPDDR4X operating at the I/O supply voltage reduced by 55%.
When evaluating and implementing a DDR4/LPDDR4/LPDDR4X interface in a system, designers face additional challenges in modeling and analyzing the memory subsystem besides the normal Signal Integrity (SI) and Power Integrity (PI) considerations. For example, BER measurements using serial link analysis techniques can only be achieved on individual channels of differential signals. For memory applications with parallel bus groups of single-ended signals, directly applying the channel analysis method is not enough and new methodologies need to be in place to guide design practice.
In this year’s DesignCon (DesignCon2019), a group of engineers at Texas Instruments shared their experience in designing and analyzing LPDDR4X interfaces in their products. Their solutions and discussions are invaluable to system designers who are looking to understand common design concerns regarding LPDDR4X:
For the details of TI’s LPDDR4 design success, visit here.