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For those of you who do wire-bond package substrate – whether you’re designing a single-chip leadframe, a multi-die memory stack, or a complex stack with wire-bonds, flip-chips, interposers, and spacers all in one – you need wire profiles.
A profile is the basic 3D path description for a bond wire. It defines the material, diameter, and direction of the bond profile. It also describes the vector that the wire moves through. To account for variations in wire lengths, one segment is always left to be calculated based on the specific wire’s length and elevation change.
Whenever you start a new Allegro Package Designer Plus substrate design, you are given a single, pre-defined wire profile: PROFILE1. When the design’s started for the first time, opening the profile editor, the profile is already there with a basic definition:
It is tempting to use this profile when you start adding wire bonds to the first die in your package. Today, in keeping with my resolutions for the new year, I want to share a few reasons why I think this is the last thing that you want to do.
This one should be self-explanatory. PROFILE1 exists in all designs, just as they all begin with a top and bottom substrate layer in the cross-section. Because this profile exists by default in every design, though, any time you move things from one design to another that references this profile (and since profile names must be unique like other library elements), the wire will take on the profile’s curvature defined in the destination drawing.
What this means is that if you changed PROFILE1 to be a reverse bond, j-loop profile in one design but left it as default in a second and didn’t verify through the 3D Viewer or Export – OLP interfaces that the wires were correct, your result could be a wildly inaccurate set of bonding tiers. Whoops! Let’s try to avoid that, shall we?
Instead, we recommend that you define your own library of profiles (or use known-good certified wire profiles from your manufacturing partner, such as the Kulicke & Soffa® profile set shipped with the Cadence® tools). Using known-good profiles with consistent naming ensures that, just by looking at the name, you know whether this profile is a forward or reverse bond, whether it is a low or high loop profile, and other characteristics. Best of all, you know that if you reuse that bond shell in another similar design, the profile curvature setups will also transfer over and function as you intended.
Setting up your profiles in a library may sound like extra work. The first time it saves you from a costly mistake in the heat of the moment to get a design out on time for a milestone, you’ll be grateful that you did!
It can be tempting just to get started with your bonding. After all, you can change the profile assignments later. Make no mistake, this is entirely truthful! Except that when you use the same profile for all wires initially, they all look the same. There’s no differentiation between the wires from the inner row of die pads going to the outer row of bond fingers. Telling the difference between the power and ground ring bonds isn’t as easy.
The only upside to this would be that it will make the wire bond tools disallow any crossing of wires, regardless of where the cross is along the wires’ lengths since the same profile wires are never permitted to cross during placement. Of course, that means that if you SHOULD be allowed to cross wires, you’ll swiftly become frustrated when the tool appears not to allow you to do so, despite assurances that your constraints are properly configured.
Changing after all the wires are added means first being able to select all the wires that you want to change to the new profile. This is simple for cases like power and ground, as you can use find by query to select all the wires on these nets with just a few clicks. For cases where you need to select all the wires connecting to a ring of fingers or die pads, the selection is much less straightforward.
Selection by path, polygon, or window will avail you little, as the inner pin tier’s wires all cross over the outer pins. You’ll get both sets of wires selected at the same time. Multiple iterations of selecting, or use of temp group, becomes a necessity. Take the below 3-tier bond out. Getting all the wires to the right profile is no trivial task!
All it takes to avoid these hassles is a little up-front planning to define and select the right profiles when adding the wires. Make defining the profiles and bond finger padstacks your first steps in the wire bond portion of your design flow. Then, select the right pads and profiles when adding the wire bonds (hint: you can use wire bond groups to create reusable sets of characteristics like Finger A + Profile B + Aligned with Wire finger rotation to make this a one-step process).
If it turns out that you need to change profiles later – maybe an ECO moves a pin from the inner to the outer ring of die pads – you need to change only one wire and adjust to minimum DRC on the pattern to complete the update of the package in under a second.
It’s a true statement, I promise. For bond wire DRCs to be accurate (not just wire-wire checks, but wire to die edge, wire to substrate (for cavity bonds), even optical wire cross-checks if you have j-loop bonds in place, the number one prerequisite is accurate wire profiles and accurate die stack height information.
Die stack information is critical, particularly if any profile definitions use percentages of the elevation change for segment description. A die characterized as having height of 10 instead of 100 will mean incorrect wire height changes. This can lead to failing to detect situations where the wire will be damaged by the mounting of a higher die in the stack or by the mold cap.
The profile is just as important. Should you leave the profile at the default new-design values, you are more than likely going to find all your wires in violation of spacing to the die edge when you first check for errors in the 3D view. The same is true when you have multiple die pad tiers. Using the same profile for both, the inner pads’ wires will inevitably violate spacing to the outer wires (since they will be at the same approximate height along their vectors). Your design will be a large mass of error markers as in the image above. Which are the real problems, which are phony? The struggle to know is very real!
Have I convinced you to join me in making this resolution for the new year? To save ourselves some collective time and energy and make sure our designs are right from the start? I hope so! But, as ever, should you have questions, please contact the support team and we’ll be happy to help you. No matter how complex your bond shell looks, the Cadence IC Packaging tools can make them a reality!