Cadence Community

IC Packagers: Optimize Display Settings for Faster Screen Redraws

By Tyler | 15 Oct 2019

While designing interposers and very high pin count device packages, as the number of objects to manipulate increases, you may notice that the display takes longer to draw. This is for a very good reason: by default, the tools will draw everything.....

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PCB | APD | SiP Layout
Machine Learning in JasperGold

By Paul McLellan | 15 Oct 2019

When I was in Tel Aviv for CDNLive Israel, I sat down with Ziyad Hanna to discuss what Cadence calls "Smart Formal Technologies". This is using deep learning techniques to improve formal verification with the JasperGold Formal Verification ...

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Jasper User Group | Jasper
DATA Pulse: Collaborate and Combine Forces – Allegro EDM Team Design

By Auromala | 14 Oct 2019

Working in an ECAD design team? Want to control access to certain design elements? Would notifications of design changes by other team members be helpful? If yes…

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allegro edm | Team design | PCB design
Arm TechCon: The Keynotes

By Paul McLellan | 14 Oct 2019

Simon Segars opened Arm TechCon with a new look, having discovered that real men have beards. This is the 15th Arm TechCon. In this post I'm going to focus on the new things that Arm announced during the keynotes. Simon Segars Back when TechCon s...

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automotive | ARM Techcon | Simon Segars | cloud | mobile | ARM
Virtuosity：Modgen简介

By Aneesh Shastry | 13 Oct 2019

半导体行业的飞速发展导致对模拟版图自动化的需求不断增长。模拟电路通常使用current mirrors和 differential pairs的结构，其中器件特性的分组和匹配至关重要。 Virtuoso通过提供高端工具来解决这些挑战，这些工具可确保在设计目标上更快地融合并实现高效的版图实现。在此博客中，我将向您概述这样一种工具-Virtuoso Module Generator，俗称Modgen。

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EAD | Chinese blog | Modgen On Canvas | MODGEN | automation | Automatic Placement | module generation | Module Generator | Layout | Custom IC Design | modgens | Virtuoso Layout Suite | Virtuoso Layout Suite XL